IP Core ARINC 818

ip core arinc 818 - IP Core ARINC818
ip core arinc 818 - IP Core ARINC818

Atomic IP Core

Great River Technology’s ARINC 818 IP Core is a simple way to implement ARINC 818-compliant interfaces in many popular FPGAs. The core combines with the FPGA’s high-speed serial tiles (e.g. GX or GT tiles) to realize ARINC 818 interfaces up to 10.0 Gbps. The IP Core can be used in different forms: transmit-only, receive-only or for both transmit and receive applications.
The core has many flexible parameters at compile time, allowing various link speeds, line segmentations and line synchronization methods. IP Core can be configured for different resolutions and pixel stacking methods. Auxiliary data transmitted can use default values (defined at compile time) or data can be updated in real time via the register interface.
ARINC 818 IP Core is delivered as encrypted VHDL. Great River Technology also offers an Airborne Atomic IP Core package including all the elements required for DO-254 certification.
Great River Technology currently offers the ARINC 818 IP Core for a wide range of Intel and Xilinx FPGAs.

Technical sheet
Description
Attributes
Reference

Applications

  • Single or Multiple Channel FPGAs
  • Channel Bonded Links
  • ARINC 818 Switches
  • Video Concentrators

Key features

  • Configurable for almost any video resolution and frame rate
  • ARINC 818 Link Speeds : 1X, 2X, 3X, 4X, 5,0 Gbps, 6X, 8X, and 10,0 Gbps
  • Pixel Types : RGB 8:8:8, ARGB 8:8:8:8, RGB 5:6:5, Mono 8-bit, “No Pack” for any pre-packaged pixel type
  • Compatible with progressive and interlaced video
  • Provides simple 32-bit pixel bus transmit and receive ports with independent pixel clocks
  • Less than one video line time on receive and transmit
  • Line Synchronization : Line-synchronous or non-line synchronous transmission; Configurable for desired pixels per line
  • Object 0 Ancillary Data : Supports real-time update of transmitter’s Obj 0 data; Setting default Obj 0 transmit data at compile-time; Complete Obj 0 data recovery by receiver
  • Provides receiver status and error detection indicators
  • Instantiation Options : Transmitter only, receiver only, or full-duplex transceiver

FPGA support :

  • Altera Arria V
  • Altera Arria X
  • Altera Stratix V
  • Altera Cyclone V
  • Altera Cyclone X
  • Xilinx Spartan-6
  • Xilinx Artix-7
  • Xilinx Kintex-7
  • Xilinx Kintex-Ultrascale
  • Xilinx Kintex-Ultrascale Plus
  • Xilinx Virtex-6
  • Xilinx Zynq
  • Xilinx Zynq-Ultrascale Plus
  • Xilinx Virtex Ultrascale
  • Xilinx Virtex Ultrascale Plus
  • Xilinx Virtex 7
  • Microsemi PolarFire

ARINC 818 protocol

ARINC 818: Avionics digital video bus

The ARINC 818 video interface and protocol standard serves high-bandwidth, low-latency, uncompressed digital video transmission.

The standard has been advanced by ARINC and the aerospace community to meet the stringent needs of high-performance digital video. The protocol was adopted, prior to its official release, by major aerospace and military programs, and has become the de facto standard for high-performance military video systems.

For more information on the ARINC 818 protocol: http://www.arinc-818.eu/en/

ARINC 818
Interface ARINC 818
Rate 5 Gbps, 10 Gbps
Supplier Great River Technology
  • IP Core ARINC 818

The IP Core combines with the FPGA’s high-speed serial tiles to realize ARINC 818 interfaces up to 10.0 Gbps

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Add-on products

ip core arinc 818 - Velocity

ARINC 818 frame grabber, generation and conversion up to 8 Gbps

Velocity

ip core arinc 818 - HS SAM 1

ARINC 818 conversion stand alone module

HS SAM

ip core arinc 818 - SAM G3 end plate

ARINC 818 stand alone converter module

SAM G3 Plus

ip core arinc 818 - Velocity Dual Channel

Carte d’acquisition 2 liens ARINC 818

Velocity Dual Channel